Below shown various GATEs with their VHDL code...
AND Gate | VHDL Code |
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sig_3_out <= sig_1_in AND sig_2_in; |
OR Gate | VHDL Code |
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sig_3_out <= sig_1_in OR sig_2_in; |
NOT Gate | VHDL Code |
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sig_2_out <= NOT sig_1_in; |
NAND Gate | VHDL Code |
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sig_3_out <= sig_1_in NAND sig_2_in; |
NOR Gate | VHDL Code |
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sig_3_out <= sig_1_in NOR sig_2_in; |
XOR Gate | VHDL Code |
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sig_3_out <= sig_1_in XOR sig_2_in; |
XNOR Gate | VHDL Code |
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sig_3_out <= sig_1_in XNOR sig_2_in; |