To keep the code modular, readable and maintainable I suggest you few tips..
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- Keep structural and behavioral entities code in separate files.
- Always use one single file for each module/entity, never code multiple entities in a single file.
- Although VHDL is case insensitive language, but it is a good idea to keep all the constants and key-words in upper case.
- Keep unique entity names, no two entity should have same name in a design.
- Keep file name same as entity name, this will help you in debugging, and will avoid you to remember file and entity name relationship.
- Some operating systems don't take more than 8 characters as file name, and terminate them with "~". If you are using such OS then make sure that your files name should not exceed 8 characters.