Lets devote some time and understand how to code various digital elements. You can code whole digital systems, once you learn coding these individual elements. Always remember, start coding only when your design activity is finished. Coding a partial designed module/project generally requires lot of re-work afterwards. Estimating your design size is very important, specially when you are targeting it for FPGA. Since in FPGAs, flipflop and logic-cells are limited, you should strictly analyze your design size.

For any FPGA design, we generally follow these steps ..
Design architecture -> Design modules-> Code modules-> Code architecture-> Integrate Design -> Verify or Test your design-> Synthesize it for targeted FPGA-> program FPGA with bit-file (bit-file is generated after synthesis). Its a good idea to run a dry synthesis on your design just after Integration (to get design size), if the design doesn't fit into targeted FPGA, this will save your verification time.

We will come back to these serious issues later also, but first lets learn coding few