Negative-edge Flip-Flop
VHDL CODE 1) flop_process : PROCESS(clk_sig, reset_sig) 2) BEGIN 3) If(reset_sig = '0') THEN 4) ff_out_q_sig <= '0'; 5) ELSIF(clk_sig 'event AND clk_sig = '0') THEN   6) ff_out_q_sig <= data_bit_sig; 7) END If; 8) END PROCESS;

Here every thing is same except a minor change at line no 5. Since we wanted to code -ve Edge flip flop, where the output "ff_out_q_sig" gets updated with "data_bit_sig" at the falling edge (1 -> 0) of the clock. we have modified the condition at line no 5 to AND clk_sig = '0' thats it!
Now the new condition is, when the clk_sig ticks and clk_sig = '0' (i.e -ve edge).