Positive-edge Flip-Flop with Chip Select
VHDL Code   1) flop_process : PROCESS(clk_sig, reset_sig) 2) BEGIN 3) If(reset_sig = '0') THEN 4) ff_out_q_sig <= '0'; 5) ELSIF(clk_sig 'event AND clk_sig = '0') THEN   6) IF(enable_sig = '1') THEN 7) ff_out_q_sig <= data_bit_sig; 8) END IF; 9) END If; 10) END PROCESS;

The figure above shows a +ve edge flip-flop with enable pin. enable, chip enable or chip-select all are same. The chip-enable pin gets third priority (reset -> clock edge -> chip-enable). This means that the output will change only when enable pin = '1'. This is archived by putting one more condition inside clock edge check i.e if conditional statement (line no 6,7 and 8).